With the growing demand for RISC-V architectures in various applications, by combining Lauterbach’s TRACE32 tools and Andes’ NCETRACE200 trace solution developers now have a deep, non-intrusive trace visibility into their System-on-Chip (SoC) to assist debug & trace, achieving higher levels of reliability, performance and efficiency in their embedded products.
AndesCore NCETRACE200 subsystem is a non-intrusive tracing solution designed for the Andes RISC-V processor portfolio that spans from small, low-power MCUs to high-performance OoO application processors.
Key features include:
- RISC-V N-Trace compatible trace encoder, timestamp generator and decoder
- Multi-core tracing, up to 8 RISC-V harts
- Configurable size Trace Buffer
- Mixed-ISA environment supported, including compatibility with the CoreSight technology by Arm.
Commenting on the collaboration Norbert Weiss, Managing Director at Lauterbach, said, “Our collaboration will provide engineers with the tools they need to maximise the potential of their RISC-V designs, fostering innovation and efficiency in embedded systems.”
Andes also expressed enthusiasm about the partnership. “Working with Lauterbach allows us to deliver a comprehensive debug and trace experience to our customers, further solidifying our position in the embedded systems market,” said Dr. Charlie Su, president and CTO at Andes Technology. “This collaboration will pave the way for innovative developments in the RISC-V landscape, supporting a new generation of embedded solutions.”
