Engineering publications brought to you by Mark Allen

ASIC & SoC

A strategy bearing fruit

Chip from Vayyar provides a high resolution, mobile and cost-effective 3D imaging solution

Cadence prototypes first IP interface in silicon for preliminary version of DDR5 standard being developed in JEDEC

UltraSoC selected by Andes for RISC-V development with trace and debug

The dangers of speculation

First integrated FPGA-in-the-loop workflow for PolarFire and SmartFusion2 FPGA development boards

Tackling congestion on programmable devices

Enabling the adaptable world

Ultra low power MCU design features MRAM

IoT apps processor boasts eight RISC-V cores

European MiniZed SpeedWay Design Workshop series

Compact dual 10A or single 20A µModule regulator powers FPGAs, GPUs, ASICs and system power