No surprise, really; that has been the timetable which the industry has set itself ever since Gordon Moore’s observation that the number of transistors on a given area of silicon was doubling every 18 months. His observation was deemed a ‘law’ by the equally legendary Carver Mead and semiconductor manufacturers have set their clocks by it.
And none more than Intel, with its ‘tick tock’ approach to scaling. In this, a ‘tick’ represented an upgrade to the microarchitecture, while a ‘tock’ was the process shrink.
But even Intel has been unable to maintain this regular process as the challenges of the Laws of Physics make moving to the next node hugely challenging. The original 18 months became two years and so on.
Moving to smaller processes has also demanded new designs. High K metal gate enabled 20nm, while FinFETs moved things onward. Now, such approaches as gate all round are being considered for 5nm and beyond.
For those manufacturing at the leading edge, another factor slowing progress has been the inability to get EUV lithography to the point where it can be used ‘in anger’.
Is Intel’s development of Fab 42 in Arizona an analogue of how hard the challenge has been? Fab 42 was announced in 2011 with a fanfare, but has remained a shell since. Only now is Intel equipping the fab and, in doing so, looking to 7nm technology, even though industry observers don’t think it has such a process ready for implementation quite yet.
While all leading edge players look to the future with enthusiasm – they have to, after all – getting there is a different matter.
