Will FD-SOI kick start Kroes' 10:100:20 plan?

Recently, ST has been developing an FD-SOI process that it hopes will provide a way to deal with such issues as leakage and performance. The process differs from those being pursued by Intel and TSMC; they are developing 3D processes using so called FinFET transistors. But FD-SOI is planar and the transistors are said to be easier and cheaper to make. Where things differ – at least for the moment – is that Intel and TSMC are targeting 14/16nm devices, but ST is working at 28nm. Is that a problem? Not necessarily; cost sensitive processes are popular for a range of applications. One of ST's problems was that, while it had the FD-SOI process, it didn't have much capacity. That problem has been solved by the licensing of FD-SOI to Samsung, which will offer it as a foundry option. Materials company Soitec has gone as far as to call the move a 'tipping point'. The interesting question is how all of this might fit into Neelie Kroes' plan to boost the market share of Europe's semiconductor industry. In her 10:100:20 plan, Kroes wants Europe to produce 20% of global chip demand within the next decade. The Electronics Leaders Group, charged with coming up with a implementation plan, believes it can be done by capturing a big chunk of the market for chips aimed at the Internet of Things and Smart devices. And FD-SOI – suited to the low power requirements of the IoT – could be the technology which enables this plan to be achieved. One thing is missing: production capacity. It's all very well Samsung offering FD-SOI as an option, but it doesn't do much in the way of boosting Europe's chip production. What might is the building of a dedicated facility for FD-SOI in Europe. Although not explicitly in the Kroes plan, there has been much discussion over the last couple of years about whether or not the EU should invest in a 450mm so called 'mega fab'. With FD-SOI now seen as a viable technology, is now the time to make that call?