Conquering DDR Memory Design and Testing Challenges

Why is this event important? DDR Memory is one of the most commonly used memory technologies in computer and embedded designs today. With system speeds ever increasing and design margins ever decreasing, digital designers need to plan even more carefully to ensure the next power on goes smoothly. Thorough Characterisation and Validation can be a time consuming and challenging process. This complimentary half day seminar aims to provide information on how a holistic approach to memory test preparation coupled with the latest tools and measurement techniques can lead to a successful outcome. Who should attend? Engineers and Engineering Managers responsible for the specification, design and test of new high speed memory, including Controller Developers, Integrators and Memory Interface Characterisation and Debug teams. What to expect? * You will learn how to measure, characterise and debug memory timing, signal integrity and protocol/functional behavior of the memory channel. * You will be shown how to characterise and validate memory controller and PHY designs, especially memory timing control state machines and delay lines. * You will learn more about cutting edge memory technologies that are defining how all this will need to be done in future designs. Register here.