Achieving system level boundary scan in different ways

Compliant devices include five primary Jtag pins/pads, namely clock (TCK), test mode (TMS), data in (TDI), data out (TDO) and reset (TRST). The TDI and TDO pins of devices are connected so as to form a boundary scan chain and all signals terminate at a Test Access Port (TAP). The increasing availability of system level interface devices – commonly known as scan 'gateways' or 'bridges' – has allowed the extension of Jtag to the system level. These devices, which in their simplest form can be considered as addressable multiplexers, allow for board to board interconnect tests for: the diagnoses of backplane interconnect failures; system testing, prior to customer shipment (including verification of firmware objects); and a reduction in the test signal infrastructure across a system backplane. While there are several TAP routing strategies that can be adopted at the system level, including 'ring', 'star' and 'multidrop', only the last, based on IEEE1149.1, is widely used for reliable system control. Within this strategy, the five primary test access signals are connected in parallel to all backplane slots within the system. Each of the slots will have a unique address consisting of six or seven address lines, providing up to 64 or 128 addresses, which will usually be hardwired within the backplane (see fig 1). Each board within the system is accessed by a Jtag/boundary scan tester which broadcasts its unique backplane address via the TDI signal line of a global scan chain (GSC). The board located in the slot corresponding to the broadcasted address will 'wake up' and allow access to local scan chains (LSCs). System level test access devices are available from a number of vendors, including Firecron and National Semiconductor. Their primary function is to provide access from a GSC to specific LSCs, which can be selected individually or daisychained together in order to provide complete flexibility for test partitioning. This is particularly useful for the in system programming of flash memory (see fig 2). Under these circumstances, the number of vectors shifted around the boundary scan chain on the board should be kept to a minimum to optimise the flash programming cycle time. Embedded control In the above scenarios, it has been assumed that an external boundary scan controller, such as a Jtag DataBlaster, is used to drive test patterns (or 'vectors') to individual boards via the GSC infrastructure. There are, however, a number of different embedded control architectures that can be implemented within IEEE1149.1 system test configurations to execute built in self test (BIST) for structural, rather than functional, testing. Discrete devices – for example, the STA101 from National Semiconductor and the JTS01 from Firecron – are driven from a host processor on a system 'shelf controller' and, while not widely used, they have been available since the late 1990s. JTAG Technologies also offers an embedded test controller as a more complete entity (pcb featuring a microcontroller, memories and programming interface) that includes a Jtag code compiler and can be built into a system. In addition, it is now possible to harness other communications ports/protocols as a conduit to access the IEEE1149.1 test infrastructure. For example, JTAG Technologies' TapCommunicator comprises gigabit Ethernet (IEEE802.3z 1998) up link and down link modules so that 'testers' and 'targets' can code and decode boundary scan applications. This technology is available as either an off the shelf Ethernet product or as IP (in the form of Vhdl or Verilog code) that can be embedded under licence into an asic or fpga. What's more, since TAPCommunicator technology is portable, it is envisaged that other communications protocols, such as CAN, Arinc and Bluetooth, could be harnessed for different applications. Indeed, SpaceWire technology has already been implemented onto TAPCommunicator to facilitate the remote testing and diagnostics of orbiting satellites. On the other hand, using embedded controller solutions allows fully independent testing, such as power on self test (POST), as the test vectors and programs are stored 'on board' the system, typically within flash memory. Failing boards can be further tested at a central facility, where net level diagnostic reports can be overlaid onto a board layout viewer such as Jtag Visualizer. The embedded controller can be located either on a single system master card or locally on multiple cards within a system. The former, sometimes referred to as a 'passive backplane – system test bus master', is more common. In this configuration, one module on the backplane is the system master, the others are slaves. The boundary scan test vectors (patterns) for testing the individual slave modules and for performing testing between modules are located within flash memory on the system master card. These vectors are transmitted via the primary Jtag bus under the control of the embedded scan controller device located on the system master card. This system level infrastructure can be used to perform a variety of tests, ranging from static structural tests to embedded at speed BIST, and can also be used for field level upgrades of system operational firmware and revisions of configuration code within plds. All systems go Customer demand has driven the rapid development of IEEE1149.1 boundary scan as the de facto standard for both system level testing and for reconfiguring applications in the field. Moreover, imaginative use of the standard has, thus far, avoided the need for a dedicated maintenance and test management bus. Finally, additional development of embedded test bus controllers has further enhanced the use of boundary scan as an effective BIST method for large scale systems and is used actively in high end military projects such as airborne radar as well as commercial communications applications. Setting standards The SJTAG Initiative Group (www.sjtag.org), working within the IEEE's Test Technology Standards Group, is working towards preparing a standard for system level Jtag. It will be based on the existing capabilities provided by IEEE1149.1, while looking forward to the capabilities offered by other emerging standards, such as 1149.7 ('reduced pin Jtag') and P1687 ('Internal Jtag'). SJTAG aims to address a number of problems faced when handcrafting system level boundary scan, namely: • Electronic cad data will rarely help you to identify constraints, such as backplane signals that must be kept in a defined state during test in order to avoid unwanted resets • It is rare that anyone designs how all the boards in a system connect together in a cad drawing. Rather, it tends to be done in higher level documentation) • The configuration of a system can change with time; boards get swapped, upgrades get installed, expansion slots get filled. So the system netlist cannot be assumed to be a static entity • Different devices and different tools all handle the multiboard, multichain scenario in different ways, so what works in one case may not work in another. James Stanbridge is sales manager UK for JTAG Technologies.