The resulting hype around this module specification is reason enough to take a closer look at this ‘ultimate’ standard for low power processor modules and to highlight the differences between it and SMARC 1.1, Qseven and others.
The Qseven and SMARC standards are both under full control of SGeT and, about a year ago, several members of the Qseven SDT.02 workgroup concluded the Qseven standard was limited because the 230pin MXM-2 connector used for signal transmission to the carrier board was unable to implement any additional signals.
For ‘real’ embedded designs, there was an urgent need to add signals which could be used by embedded hardware, exceeding the capacity of the Qseven connector. As an alternative, the MXM-3 connector, with 314pins, was discussed; something which had already been in use for the SMARC 1.1 standard. At the same time, SGeT workgroup SDT.01 was discussing and defining the next generation SMARC standard. Delegates from the Qseven workgroup concluded the market was too small for two competing standards using the same connector but with different pin-outs, and therefore joined SDT.01 to help with the definition of the ‘ultimate standard’ for low power processor modules.
While important signals for embedded processor applications should remain available, many older signals were removed in order to free pins for new interfaces to provide faster speed and lower pin count. Backward compatibility from SMARC 2.0 to SMARC 1.1 was not a target and has not been achieved. However, the standard now supports ARM/RISC and x86 processors.
The SMARC standard features two module sizes – 82 x 50mm and 82 x 80mm – providing processor module manufacturers with the flexibility to develop modules with the right mix of features and to find the optimum trade off between cost and performance.
The small format provides enough space for single-chip SoCs, such as the Intel Atom or the i.MX6 from NXP, as well as DRAMs and flash memory. If the module is targeted at higher functionality, then the need for further controller chips may require the larger module format. This is likely to be the case when functions such as WLAN, Bluetooth or 3G/4G data communication are required, so a radio module will be added and the module standard specifies the placement of the antenna connectors.
Compared to the SMARC 1.1 specification, new interfaces have been added for revision 2.0. These include a second LVDS interface, which can be used to drive high resolution LCDs in a two-channel arrangement or operate two fully independent displays on single LVDS channels. The new standard also allows alternative use of the LVDS pins for DSI or embedded DisplayPort (eDP). In order to achieve this, the parallel RGB lines for smaller LCD had to be removed, but these are no longer required for modern displays.
The standard also specifies a combined HDMI/DP port – designated DP++– because it implements the signals for DisplayPort, HDMI and DVI. When used with the HDMI and LVDS ports, it opens the possibility of driving up to three independent displays.
While SMARC 1.1 only provided one Gigabit Ethernet port, this has been increased to two because modern applications are likely to need two LAN ports in order to keep the sensor and management domains apart in IoT gateways. Real-time trigger signals have been added to both Ethernet ports to give them RT capability, according to IEEE1588.
SMARC 2.0 provides up to four PCI Express interfaces, which will allow an optional PCIe x4 operation and a substantial performance gain. The situation is similar for USB, with up to six USB 2.0 and up to two USB 3.0 ports. This underlines the suitability of the SMARC standard for x86 platforms, because these CPUs are always hungry for USB ports. For ARM/RISC platforms, there are two USB ports which optionally support Client functionality. For x86 processors, one of the two SPI buses has been provided with optional eSPI functionality. Two audio interfaces can be used in parallel – one for I2S audio as used by ARM processors, and one for HD audio, the standard codec for x86 CPUs.
Support for the 8bit MMC/SD card interface has been dropped, but the 4bit SDIO continues to be available for SD cards. While the parallel camera interface had to be removed to allow for the interfaces described above, the standard continues to provide two MIPI CSI-2 interfaces – one with two lanes and a second with four lanes. This makes SMARC 2.0 the standard with the widest and most flexible camera interface of all established COM standards. But it also provides a SATA port, 12 GPIOs, two CAN buses and four UARTs, all important for embedded applications.
One of the most ‘future-proof’ parts of SMARC 2.0 is the number of ‘reserved’ lines on the MXM-3 connector, intended for new and additional interfaces. With the ability for future extension, SMARC 2.0 can be improved without making today’s carrier boards and/or modules obsolete. No hardware designed to SMARC 2.0 will be wasted when the standard is revised; on the contrary, the standard provides for built-in upgradeability, protecting investments.
SMARC 2.0 module from MSC with NXP i.MX6: MSC SM2S-IMX6
Avnet Embedded and MSC Technologies have announced a SMARC 2.0 module based on NXP’s i.MX6 application processor, and have developed a suitable Mini-ITX format carrier board. The MSC SM2S-IMX6 supports quad, dual and single core CPUs, as well as the improved data throughput and higher graphics performance of the Plus processors. The module comes in a 82 x 50mm format and provides up to 4Gbyte of DRAM and up to 64Gbyte of eMMC flash. An integrated Micro-SD card slot or the eMMC flash may be used for booting and can contain the operating system. Displays of up to full HD resolution can be driven via the HDMI and LVDS interfaces and the module supports PCI Express Gen. 2.0 and SATA II up to 3Gbits, as well as 5x USB 2.0 Host, USB 2.0 OTG, gigabit Ethernet, four UARTs, two SPI ports, two I²C and two CAN interfaces. The MIPI CSI-2 interface can be used as camera input.
The module will be available for use in temperatures ranging from -40 to 85°C, as well as for commercial temperatures.
The SMARC 2.0 module uses the same hardware core as MSC’s Qseven and nanoRISC modules, both based on NXP’s i.MX6 processors. Software support is available, from bootloader to operating system to drivers and tools, including Yocto Linux and Android. Windows Embedded Compact (WEC2013 and WEC7) and further Linux variants will be added later on.
The MSC SM2-MB-EP1 carrier board, which comes in the mini-ITX format, measures 170 x 170mm and gives access to most SMARC 2.0 features. With a range of interfaces, it is not only a good choice for evaluating SMARC 2.0 modules, but may also for low volume applications.
Samples of the MSC SM2S-IMX6 module will be available when SGeT publishes the full SMARC 2.0 standard.
We consider SMARC 2.0 to be the best and most future-proof standard for embedded modules in small form factors and appreciate the support of all leading Computer-on-Module makers. And MSC has already begun the design of its second SMARC 2.0 module, which will be based on the next generation of Atom processors from Intel.
SMARC 2.0 carrier board from MSC in Mini-ITX format: MSC SM2-MB-EP1
Author profiles
Peter Eckelmann is product marketing manager at MSC Technologies and Tim Jensen is business development manager computing solutions at Avnet Embedded EMEA.
