Converting expectations

The push to improve the precision of instrumentation systems has led to performance improvements in d/a converters beyond 16bits, a benchmark previously achieved with cumbersome, expensive and slow Kelvin-Varley dividers. Over time, however, the definition of what constitutes a precision d/a converter has changed as markets and technologies have evolved. Advances in semiconductor processing, d/a converter design and calibration techniques are enabling highly linear d/a converters which are stable and fast settling, while delivering a 20bit performance which is better than 1ppm. These small ics have guaranteed specifications, do not require calibration and are easy to use. Applications for a 1ppm d/a converter vary from gradient coil control in medical MRI systems to precision source and positioning in mass spectrometry and test and measurement applications. Performance measures The circuit in Fig 1 delivers 1ppm performance; its key specifications are integral nonlinearity, differential nonlinearity and a peak to peak noise of 0.1Hz to 10Hz. In Fig 1, U1 is a 20bit d/a converter with 1ppm linearity specifications. U2, a precision dual amplifier, is a force-sense buffer for the d/a converter reference inputs. U3, a precision output buffer, is required for load driving; its key requirements are similar to that of the reference buffers, including: low noise; low offset voltage; low drift; and low input bias current. Even though precision sub ppm components are available, building a 1ppm system is not a task that should be taken lightly. The major contributors to errors in 1ppm accurate circuits are noise, temperature drift and thermoelectric voltages. * Noise To enable a true 1ppm system, noise contributions needs to be minimised. The noise spectral density of U1 is 7.5 nV/vHz. U2 and U3 specify noise density of 2.8 nV/vHz, much lower than the d/a converter's contribution. Wideband noise can be filtered, but low frequency noise in the 0.1Hz to 10Hz range (1/f) cannot and the most effective method of minimising this is in component optimisation and selection. U1 generates 0.6µV p-p of noise in the 0.1Hz to 10Hz bandwidth, much less than the 1LSB level (19µV for a ±10V output). The design target for 1/f noise in the system should be approximately 0.1 LSB or around 2µV. The three amplifiers in the signal chain generate a total of approximately 0.2µV p-p of noise at the circuit output. Add this to the 0.6µV p-p of U1 and the total expected 1/f noise is 0.8µVp-p. * Temperature drift Temperature drift is another major source of error in precision circuits. U1 exhibits a temperature coefficient of 0.05ppm/^°C. U2 drifts at 0.6µV/^°C, which introduces an overall 0.03 ppm/^°C drift into the circuit. U3, meanwhile, contributes a further 0.03 ppm/^°C of output drift. These contributions add up to 0.11 ppm/^°C. For scaling and gain circuits, low drift, thermally matched resistor networks are recommended, such as Vishay series 300144Z and 300145Z. * Thermoelectric voltages Thermoelectric voltages are the result of the Seebeck effect, where temperature dependent voltages are generated at dissimilar metal junctions. The generated voltage can be anywhere between 0.2µV/°C for a copper to copper junction and 1mV/°C for a copper to copper oxide junction. Thermoelectric voltages manifest as a low frequency drift similar to 1/f noise and can be greatly reduced by keeping all connections clean and oxide free as well as shielding circuitry from air currents. Fig 4 shows the difference in voltage drift between a circuit that is open to air currents and a circuit that is shielded. Long term stability Precision analogue ics are stable devices, but do undergo long term age related changes. The d/a converter's long term stability is typically better than 0.1ppm/1000hr at 125°C, but the aging is not cumulative; rather, it follows a square root rule. If a device ages at 1ppm/1000hr, it will age at v2ppm/2000hr, v3ppm/3000hr and so on. This is typically 10 times longer for each 25^°C reduction in temperature, so, when operating at 100^°C, one can expect ageing of 0.1ppm over 10000hrs – approximately 60 weeks. If this is extrapolated, the device can be expected to age by 0.32ppm over a period of 10 years. Circuit construction and layout In a circuit where such a high level of accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the pcb such that the analogue and digital sections are separated and confined to separate areas of the board. There should be ample power supply bypassing of 10µF in parallel with 0.1µF on each supply located as close to the package as possible. The capacitors should have low effective series resistance and low effective series inductance. A series ferrite bead on each power supply line will further help to reduce high frequency noise getting through to the device. The power supply lines should use as large a trace as possible to provide low impedance paths and to reduce the effects of glitches on the power supply line. Shield fast switching signals, such as clocks, with digital grounds to avoid radiating noise to other parts of the board; they should never be run near the reference inputs or under the package. Avoid crossover of digital and analogue signals and run traces on opposite sides of the board at right angles to each other to reduce the effects of feedthrough on the board. Fig 2 Building a 1ppm a/d solution A typical contemporary 1ppm a/d solution consists of two 16bit d/a converters – one major, the other minor. Their outputs are scaled and combined to yield increased resolution. The output from the major d/a converter is summed, with the output from the minor device attenuated so that it fills the resolution gaps between the major d/a converter's LSB steps. The combined outputs need to be monotonic, but not extremely linear, because high performance is achieved with constant voltage feedback via a precision a/d converter, which corrects for the inherent component errors. Thus, circuit accuracy is limited by the a/d converter, rather than the d/a converters. However, because of the requirement for constant voltage feedback and the inevitable loop delay, the solution is slow, potentially requiring seconds to settle. Although this circuit can achieve 1ppm accuracy, it is complex, likely to require multiple design iterations and requires a software engine and precision a/d converter to achieve accuracy. To guarantee 1ppm accuracy, the a/d converter will also require correction – since an a/d converter with guaranteed 1ppm linearity is not available. The block diagram shown here illustrates the concept, but the actual circuit is far more complex, with multiple gain, attenuation and summing stages and many components. Digital circuitry is also needed to facilitate the interface between both d/a converters and the a/d converter; not to mention the software required for error correction. Author profile: Maurice Egan is a product applications engineer for precision converter products with Analog Devices.