Jitter is a familiar term that can be used to cover a range of problems relating to timing in electronic circuits. Phenomena described as 'jitter' may be measured in either the time or frequency domains; in each case, multiple types of timing faults can be described as jitter.
A system's signal integrity will be impaired by jitter to a greater or lesser extent, depending on the magnitude of the jitter and the system's operating speed. In high data rate applications, designers are commonly required to attenuate jitter. But, to do so, it is necessary to know how the jitter is generated.
There are many potential sources of jitter, so isolating the most important sources is not always straightforward. However, the main sources include:
• the power supply: ripple current, parasitic capacitances and magnetic interference can all disturb timing circuits
• crystal oscillators: a certain level of jitter will be inherent to the device and this might be magnified over time or temperature
• PCB tracks: crosstalk might interfere with timing operations
• PCB components: magnetic devices are particularly prone to generating interference that causes jitter
Fortunately, various methods can help to reduce the magnitude of jitter generated by these sources.
The first is one that designers should already be implementing – good board layout. It is sensible to start with this, since curing jitter in this way brings no additional BoM cost. Layout practices that help to reduce jitter include:
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Managing the routing and termination of long tracks. At high frequencies, a simple PCB track acts like a transmission line in a communications network and can, thereforem give rise to crosstalk and signal attenuation. The board designer must take care to match the impedance at each end of each track and route signal paths properly so as to minimise crosstalk (for instance, by using twisted pairs).
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Stacking layers appropriately. In a multilayer PCB, small signals should be accommodated in the middle layers, whilst the top and bottom layers should contain the power and ground planes.
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Isolating the power supply. A voltage regulator's potential to disrupt a timing circuit can be gauged by studying its Power Supply Rejection Ratio (PSRR) specification. An isolated copper area – an 'isolated power island' – separates noisy power supplies from the main power plane with capacitors connected in parallel and a ferrite bead in series.
There are limits to how layout modifications can affect the disturbance caused by jitter. In particular, mechanical or electronic design requirements may prevent the designer from implementing an optimal layout, in terms of interference. Product marketers might, for example, place a higher priority on size reduction than on noise reduction, whilst the I/O configuration to and from the main controller or processor might dictate the routing of critical tracks.
This means other methods may need to be adopted to avoid distortion of high speed timing signals. One is to use a Phase-Locked Loop (PLL) timing device to attenuate jitter. Discrete PLLs are widely used to provide a clean clock signal in high-speed applications, but it is important the PLL is used correctly; in particular, its bandwidth must be optimised.
A PLL's output jitter depends on two things: imported reference noise; and internal voltage controlled oscillator (VCO) noise. The first is an accumulation of jitter inherent in the reference timing source, plus noise from the PCB and the power supply. VCO noise, meanwhile, consists of noise from the loop filter and VCO amplifiers, as well as noise from the power supply.
If the designer reduces the loop filter's bandwidth, then more of the jitter generated by the reference clock will be attenuated. So, if a greater part of the total jitter comes from imported reference noise, a low PLL bandwidth is recommended.
But this cannot be applied universally. In general, decreasing the PLL bandwidth tends to increase VCO noise, so the PLL's bandwidth needs to be balanced to minimise the total effect of VCO noise and imported reference noise. The decision about the extent to which PLL bandwidth should be decreased should be made on an application basis.
This raises the issue of VCO selection: should an external VCO be used or should a PLL with an internal VCO be chosen? An external VCO brings the freedom to choose a device with the best specifications and performance, but the device may be more sensitive to board level noise and to noise generated by components in a discrete loop filter.
Equally, a PLL with an integrated VCO could have external loop filter components which are sensitive to noise, causing timing inaccuracy. Again, the decision must be made on a case by case basis.
The use of a high quality PLL can achieve a high degree of jitter cleaning in high speed clock signals. The Pure Edge series of PLLs from ON Semiconductor is intended for use in LVPECL applications operating at between 2.5V and 3.3V. These devices offer typical output jitter of less than 2ps, making them suitable for most networking applications and for SONET and 10Gbit/s Ethernet equipment.
It is possible to achieve even lower levels of jitter through the use of cascaded PLL jitter cleaners (attenuators). This technique enables the designer to optimise the bandwidth for each of multiple PLLs and to realise timing circuits with jitter specified at the level of hundreds of femtoseconds.
Cascaded PLL ICs support a crystal input, as well as an external oscillator input. They typically feature up to 10 outputs to allow a full clocking system to be built.
Examples of this type of device are the MAX24605 and MAX24610 from MicroSemi. These integrate a digital PLL and two independent analogue PLLs and feature output frequencies of up to 750MHz.
In jitter cleaning applications, both digital and analogue PLLs are used in tandem. The advantage of the digital PLL is that its bandwidth is programmable between 4Hz and 400Hz, and a digitally-controlled oscillator makes it possible to implement frequency steering in the digital PLL. The provision of two analogue PLLs enables the generation of two frequency families from the same reference clock, or from two different reference clocks. The MAX24605 and MAX24610 feature a serial peripheral interface and on-board EEPROM provides for self configuration after power up. The use of such jitter cleaning devices enables the designer to realise a timing circuit with jitter as low as 300fs.
The approach to jitter depends on the requirements and limitations of the application. For some, a specific low jitter timing device might not be necessary because good layout practice alone can reduce jitter to an acceptable level.
In applications which require a PLL, the designer must take care to specify the bandwidth correctly. In the most extreme cases, ultra low jitter can be achieved through the use of a dedicated jitter cleaning device based on the cascaded PLL topology.
Pawel Kaczynski is central applications manager with Future Electronics EMEA's Advanced Engineering Group.
