According to Moore: “Making the steps from one technology node to the next is becoming increasingly difficult and more expensive. I don’t know how much longer it can continue.”
Could we be seeing the ‘end of scaling’ within the next ten years?
At this year’s imec Technology Forum, which awarded Moore its ‘Lifetime of Innovation Award’, the focus was on how the semiconductor industry should respond to the end of traditional scaling.
For more than 50 years, scaling has addressed issues such as cost, area, power and performance. Until recently, Moore’s Law held firm; new systems built from smaller chips delivered more functionality and performance.
Consensus was that scaling had become far harder beyond the 28nm node and that chip manufacturing was not only becoming more expensive, but scaling was, itself, also becoming increasingly difficult. As a result, there has been a focus on the use of new materials, of double and quadrupling patterning and the development of new architectures, such as FinFETS.
“The semiconductor industry is mature and research and development spending is under pressure,” suggested Gary Patton, GlobalFoundries’ CTO and senior VP of worldwide R&D. “Scaling has slowed dramatically as the cost of design has gone up, but our customers continue to scale at the leading edge.”
Qualcomm’s VP of global operations Roawen Chen said that pursuing Moore’s Law was no longer unconditional. “We no longer have to move to the latest node; that decision is more dependent on the company’s business model. The move to smaller nodes is slowing, but it is not over. EUV and material innovations will be key drivers.”
Luc van den Hove, imec’s president, warned that, should semiconductor innovation slow significantly, the impact on the electronics industry would be profound.
“Scaling will have to continue if we want to deliver the enormous computing power the IoT calls for,” he said. “Traditional growth drivers are no longer working.”
According to Chen: “5G is going to be as disruptive as data was to the mobile phone. It offers an explosion of connectivity and will fuel growth going forward. Whether it’s high performance image processing or real time decision making, there are a lot of people out there looking for a different value proposition.”
Engineers have to work harder to get additional gains out of new nodes and have developed ‘scaling boosters’, which take into account the requirements of design units such as standard cell and memory bit cells, as well as developing different combinations of fin heights and widths, for example.
Another option has been stacking multiple front end layers, although enabling more devices to be stacked in the same space comes with more complex fabrication and expense.
These techniques have helped keep the gap between true Moore scaling and the actual gains to an acceptable level, but that is becoming harder to achieve. So is Moore’s Law dead?
“Traditional scaling is ‘morphing’ to allow for growing complexity and several technology options are available,” according to van den Hove. “We will evolve from FinFETS towards horizontal and even vertical nanowires, which will bring us down to the 3nm generation, if not a few generations more. To achieve this we will need effective lithography and I believe EUV is the only effective lithography going forward.”
According to An Steegen, imec’s senior VP for process technology: “Why would Moore’s Law be dead? While there may not be the application drivers of the past, just look at the explosion in data traffic enabled by the IoT.
“This will require CPU power and storage capacity; even IoT devices will need a degree of CPU capacity. So I think there will be more than enough drivers for the more advanced nodes, especially in the server and mobile domains.
“From the application driver perspective, Moore’s Law remains very much alive. I think the problem is the technology itself. Are the expectations for power, performance and area now becoming unobtainable with current technology and does this mean there is not enough incentive, from a design perspective, to move to the next node?”
Steegen suggested that while designers like heavy scaling, where devices shrink while doubling the number of transistors, over the past 10 years or so, the industry has not followed that path. “Instead,” she said, “we have been confronted with dark periods – dark silicon – where both voltage and transistor scaling have not gone hand in hand. In fact, we are having to look at turning off certain cores in order to meet power density targets.
“So, from a technical perspective, how can we include the necessary features to support future technology roadmaps?”
“Looking at the near term, we can innovate at many levels, including advanced lithography, novel architectures and innovation at the circuit level.
“We need EUV lithography now. The industry wants a 50% die cost reduction per node, but multipatterning immersion lithography will only give a 30% reduction. Scaling boosters – intermediate metal levels – will help to shrink die size, but they will increase cost.
“Getting that 50% die cost reduction will need innovation at the design level and extra effort. If we put it all together, we can achieve a 50% cost reduction from 10nm to 7nm.”
Solutions exist, such as stacking multiple front end layers, new materials and circuit level innovations.
However, within a few years, it is likely that we will have reached the limits as to how small critical features can be made while still retaining working CMOS transistors.
Steegens asked: “How long can FinFETs last? They will be adopted for 10nm because they bring a 25% performance increase, as well as a 40% reduction in power. But they can’t meet performance-power requirements at 7nm. We will need devices which can improve the electrostatics of transistors. At imec, we’re looking at lateral horizontal nanowires, which will open the design space and provide a migration path to 5nm.”
Traditionally scaling has been focused on transistors. “In the future,” Steegens contended, “there will be a need for more intense co-design of systems and technology and a move towards specialised high level functions or building blocks. We will need to develop speciality technologies for devices like mobiles, cameras and sensors.”
To that end imec is looking beyond traditional CMOS transistors and at spinwave devices, for example, that exploit an electron’s spin. With these approaches, it may be possible to create devices that are both more compact and energy efficient, as well as using fewer components.
Going forward, scaling is expected to be more of a system level concept, according to Steegens. The more abstraction levels you cross, the higher the potential wins.
“Further out,” she asked, “are there more disruptive features? In memory caches, for example, we can replace 6T SRAMs with one transistor and a stacked magnetic tunnel junction. This brings a fourfold area benefit. Other drastic changes include vertical FETs.”
There needs to be a move away from a ‘one size fits all’ concept and as applications are upgraded, so the focus is likely to change. Some systems will benefit from lower power, others from more memory or higher I/O throughput.
“Stacking can also bring advantages,” Steegens contended. “We could start thinking about using the right technology for the right block, then stacking them.”
Developing these technologies will depend on it being done cost effectively and will require new business models and the growth in specialised blocks could result in a whole new ecosystem.
“There are devices beyond CMOS,” Steegens concluded, “and the industry has always managed to emerge from periods of dark silicon.”
