Power in the bank
Best practice in optimising fpga designs for power consumption. By Alix Coxon.
Benefiting from a focus on power optimisation, the latest 65nm fpgas consume up to 80% less power than their 90nm predecessors. Improvements in system level power consumption have been realised by simplifying power management and by providing different power saving modes. Yet, almost every decision the system designer takes has the potential to degrade the silicon designer’s work.
FPGA power consumption has two components: dynamic and static power. Dynamic power is dissipated when signals charge capacitive nodes. Static power, on the other hand, is dissipated either as leakage current or as bias current.
As transistor dimensions shrink, dynamic power improves, but static power increases because smaller transistors leak more. As a result, static power is becoming an increasingly large fraction of overall power consumption.
