USB 3.0 and PCIe 3.0 set to play an embedded role in mobile devices.

The development highlights how hybrid products are being created by embedding wireless ics into existing consumer devices. Android cameras can transmit high resolution photos and video directly to social media sites without needing an intermediary pc or tablet. Moreover, mobile devices are driving wired interface developments, including the Universal Serial Bus (USB) and the Peripheral Component Interconnect Express (PCIe), more commonly associated with moving heavy data payloads over computing backplanes. USB has long been embraced by mobile consumer devices for downloading music and video and for offloading content. Downloading music and video onto the device remains a requirement but, with Wi-Fi and faster mobile data services, content is increasingly streamed to the device. However, with 8Mpixel cameras now commonplace on smartphones, the offload requirements of high resolution digital images and video continues to grow. The latest USB 3.0 standard, to appear in handsets this year, supports 5Gbit/s. USB 3.0 also handles more power; 4.5W, compared to the 2.5W of USB 2.0, enabling faster charging. PCIe 3.0, meanwhile, runs at 8Gbit/s and is the standard I/O bus for servers, workstations, pcs and laptops. "All those applications need to connect to I/O media, whether it is Ethernet, graphics, storage, communications or Infiniband," said Al Yanes, president of the PCI Special Interest Group (PCI-SIG). PCIe supports single lanes, like USB, or x2, x4, x8 or x16 lane configurations. While it can go to 32 lanes, this is rarely needed. The next generation of the standard – PCIe v4.0 – will support 16Gbit/s lanes and will be available from 2016. USB 3.0 and PCIe 3.0 are set to play an embedded role within mobile devices. The SuperSpeed InterChip (SSIC) interface is based on USB 3.0 and is the follow on to the High Speed InterChip (HSIC) interface that connects ics within mobile devices. HSIC, based on USB 2.0, operates at 480Mbit/s. While PCI-SIG is translating PCIe 3.0 for use within mobile devices, it has no legacy within the sector, unlike USB. Handsets use the Mobile Industry Processor Interface (MIPI) Alliance's interfaces developed around the mobile application processor, with several MIPI point to point interfaces defined. These include the link between the mobile application processor and the baseband processor, the link to the device's camera sensor – the latest being CSI3, which supports 20Mpixel sensors – and the DSI-2 display interface. In particular, two physical (PHY) devices – D-PHY or the M-PHY – are used by MIPI. M-PHY is the faster of the two (up to 5.8Gbit/s, compared to D-PHY's 1Gbit/s). M-PHY links the handset's application processor to the radio, display and camera sensor, as well as supporting the low latency interface (LLI) for memory. And it is the M-PHY on which the USB 3.0 based SSIC and PCIe 3.0 protocols will run. The motivation is to benefit from the huge amount of software and applications developed for USB and PCIe, while running them on M-PHY, which has a lower power consumption than the USB or PCIe PHYs. "There is tremendous [PCIe] software developed over the last decade,"said Mark Fu, senior director marketing at Cypress Semiconductor. When PCIe was developed, care was taken that existing PCI software would work over the new standard. "The beauty of PCI and PCIe is that, at the software level, it is transparent," said Fu. "Everything has been worked out at the physical layer." The USB and PCIe groups, working with the MIPI-Alliance, seek the same goal. A Gear 1, single lane M-PHY consumes a quarter of the power of a USB 3.0 PHY, while offering a speed of 1.25 to 1.45Gbit/s. "You get power reduction and [die] area reduction, but still have plenty of throughput," said Eric Huang, senior product marketing manager at Synopsys. Gearing up Two faster M-PHY Gears were defined by the MIPI Alliance in 2012: Gear 2 is a single lane at 2.5 to 2.9Gbit/s, and Gear 3 is a single lane at up to 5.8Gbit/s. "This [Gear 3] is faster than USB 3.0, which is at 5Gbit/s," said Huang. "This is good because you don't want to be the [speed] bottleneck, but you do want to provide the minimum power." The power consumption for the 5.8Gbit/s M-PHY is 70% less than that drawn by the USB 3.0 PHY. A PHY adaptor layer, known as the PIPE 3.0 to M-PHY bridge, is needed for the SSIC standard to run on M-PHY. The bridge translates the USB 3.0 protocol onto the M-PHY hardware. The same strategy is being pursued by the PCI-SIG to run the PCIe 3.0 protocol on M-PHY. Here, a logical PHY – the equivalent of the bridge – translates between PCIe 3.0 and M-PHY. "Our [PCIe 3.0] PHY is designed for servers and pcs and it runs fast," said Yanes. "Obviously, for mobile and handhelds, the focus is on low power." PCI-SIG thought about developing its own lower power PHY for mobile, but chose instead to port PCIe onto M-PHY. "The migration with PCIe will increase the adoption of M-PHY and will allow expansion into other areas, for instance [for] the display," said Bob Feng, senior technical marketing manager at Xilinx. "There has been tons of software applications/drivers written for PCIe based display controllers. Having MIPI with mapping of PCIe will help those applications/drivers to be leveraged." Huang views the SSIC and PCIe developments for mobile as competing ventures. That said, a Wi-Fi chip developer will need to support both. "I [ as a chip maker] am going to put on as many interfaces as I can so that I can get the chip into the most products," said Huang. The Wi-Fi chip will need a USB 3.0 PHY and a PCIe 3.0 PHY, whilst supporting SSIC and PCIe 3.0 over M-PHY. This will allow the chip maker to target its product as add on after sales to tablets and laptops as well as within embedded mobile designs. Ultimately, the work being undertaken by the two groups and the MIPI Alliance will enable the multiplexing of an M-PHY to support either standard, thereby saving PHY hardware. Huang believes SSIC has at least a year's lead on PCIe 3.0 running over M-PHY: "If SSIC really takes off, it is possible that it will crowd out the mobile PCI Express." Synopsys says it will start testing SSIC as soon as it gets its hands on the first M-PHY based silicon. It is aware of at least a dozen chip design starts using SSIC in 2013, both mobile application processors and connecting ics. "Maybe in 2014, customers will have the parts, with real products in 2015," said Huang. Cypress' Fu also believes it will take time for PCIe to be adopted within mobile devices. "We talk to a lot of customers in mobile and PCIe is not something they are constantly considering as a future interface," said Fu. "But the jury is still out." Meanwhile, Yanes said the PCI-SIG group, working with the MIPI-Alliance, hopes to have the PCIe 3.0 mobile specification done in the first quarter of 2013.