Will devices such as Freescale's Kinetis L range spell the end for the 8bit mcu?

"In our view, 8 and 16bit development has reached the end of the road. Those architectures simply can't keep up as the Internet of Things gains traction," said Geoff Lees, general manager of Freescale's Industrial and Multimarket mcu business. However, until recently, 32bit offerings – not just those from Freescale – haven't competed with 8bit parts directly. But the launch by Freescale of the Kinetis L series is set to change that. It's fair to say the company is pitching these devices squarely against the 8bit competition. Freescale isn't alone in pursuing 8 and 16bit applications with a 32bit mcu. Jan Jaap Bezemer, director of marketing for NXP's mcu business line, said: "NXP is preparing to launch a series of Cortex-M0+ mcus by the end of 2012. Together, NXP's Cortex-M0 and Cortex-M0+ microcontrollers will provide the broadest range of options for 8 and 16bit applications." What has made the difference is the development by ARM of the Cortex-M0+ core (see fig 1). The Cortex-M0+ is said to consume much less energy than any 8 or 16bit processor currently available, while delivering far more performance. And this allows Freescale to offer some devices in the Kinetis L family at a similar price to that of an 8bit mcu. Jim Stuart, Freescale's consumer and industrial mcu marketing manager in Europe, said 32bit mcus will bring a range of benefits to existing 8bit users. "Apart from software architecture and programming benefits, users also get reductions in power consumption and code size." Stuart said choosing the right 32bit architecture has been important. "While it might have been an obvious decision to go with the Cortex-M0, that core has some drawbacks for this particular target market, including power consumption. So we started working with ARM to develop a core with best in class performance and an energy efficiency better than that of the best 8bit parts." The result is the Cortex-M0+ core, announced by ARM at the 2012 Embedded World exhibition. Richard York, director of product marketing with ARM's processor division, said: "We looked at things which the M0 didn't address. We have developed a core which is 50% more energy efficient than the M0, but which has an almost identical gate count – and there's a 10% increase in performance at the same clock speed." The M0+ core is rated at 1.77CoreMark/MHz, with an energy efficiency of 42.14CoreMark/nA – both values significantly better than the nearest 8 and 16bit competitors. Lees said the M0+ core is 'strategically important'. "We're looking at giving our 8 and 16bit customers a worthwhile step into the 32bit market. And cost is a 'must have' to convince them to start evaluation." Stuart said the Kinetis L family had been designed with four supporting pillars, all focused on low power. "The first pillar is the Cortex-M0+ core itself, which we think is the best core for low power applications. Then there's an ultra low power mode in the device. This is not just 'run, wait, sleep'; there's a further mode which allows different areas of ram to be enabled and for the speed at which the device returns to run mode to be selected." Stuart said the third pillar is the energy saving architecture. "The Kinetis L family is being manufactured on a 90nm process," he said, "and features thin film flash technology. Within this, we're using clocking and gating techniques and adding a bit manipulation engine." In Stuart's view, the Cortex-M0 core is not good at 'read, modify, write' operations. "The bit manipulation engine improves this by reducing code size and cycles for bit oriented operations to peripheral registers." A further addition is a crossbar bridge, which provides multiple paths between the cpu, memory and peripherals. "It's useful," Stuart continued, "when the cpu goes into stop mode, but you want to have data moving between different areas." Finally, the Kinetis L family features a range of energy saving peripherals. "Before," said Stuart, "when the cpu went into stop mode, nothing worked except for the interrupts. However, there's often the need for autonomous peripherals. For example, you might want to continue to take a/d samples, average them and use dma to move the value to memory. And, after a given number of dmas, wake up the cpu." Getting designers to move away from 8bit mcus will be a challenge, but price will be one of the factors which influences the decision. "We're being pushed on price all the time by our customers, whatever the part," Stuart admitted. "But the use of 90nm process technology means we can create an 8bit type family and hit the price point." Designers are also mindful of energy consumption and this is another area where the L series is expected to compete. "We're also being pushed on power consumption," Stuart continued, "and devices from the L series will help battery powered equipment to last longer or to run from smaller batteries." The increased processing power of the M0+ core will also bring new opportunities to 8bit applications. "Although the L series can run at up to 48MHz," Stuart pointed out, "most users won't run them that quickly; 20MHz will be more likely. But designers can take advantage of the core's energy efficiency and run at 48MHz in bursts." Looking to ease the transition to 32bit processing, Freescale will be offering some members of the L series in packages compatible with its SO8 range of 8bit mcus. And it has also launched the Freedom development platform. This low cost board, which follows the Arduino form factor, has an integrated USB debug interface, a virtual serial port and classic programming and run control capabilities. "We're not aiming this at M0 customers," Stuart asserted, "we're after 8 and 16bit users." Devices in the Kinetis L family will be available on 25 September. "We had planned to launch with engineering samples," Stuart said, "but development has gone so well that we are launching full production quality parts." The first members to be available will be the L0, L1 and L2 ranges. The entry level device will be the L0 family (see fig 2), with from 8 to 32kbyte of flash and supplied in 4 x 4mm qfn packages, compatible with SO8P parts. The L1 family will offer from 32 to 256kbyte of flash, adding communications and analogue peripherals to L0 features. The L2 family will add USB2.0 functionality. Further devices will be available early in 2013, including the L3 and L4 variants. The L3 adds support for segment lcds to the L1 feature set, while the L4 adds segment lcd support to the features of the L2.