A/D converter achieves record low power consumption of 1.7mW

The device targets wireless receivers for next generation high bandwidth standards such as LTE advanced and the emerging generation of Wi-Fi (IEEE802.11ac). SAR a/d converters are suitable for a variety of wireless applications as they provide high power efficiencies and a small form factor. They are frequently the preferred architecture for applications with moderate resolution and sampling frequencies. However, wireless receivers for next generation high bandwidth standards such as LTE advanced and the new generations of Wi-Fi require much faster a/d converters. According to Renesas and imec, the newly developed architecture addresses this need. The device is an ultra low power (1.7mW) high resolution (11b) fully dynamic, two step interleaved pipelined SAR a/d converter achieving a record power efficiency of 10fJoule per conversion step at a sampling speed as high as 250MS/s. Renesas and imec describe this as a 'spectacular increase of the speed and sampling frequency, which are both an order of magnitude better than state of the art available a/d converter IP blocks'. The result has been achieved with a new converter architecture based on prior a/d converter designs from imec which exploit modern advanced cmos technologies. The design uses completely dynamic circuits, so that the power consumption scales linearly with the sampling frequency and is implemented with a maximum amount of digital content, leaving the comparator as the only analogue building block. The prototype has been manufactured in 40nm cmos with a core chip area of 0.066mm². Measurements show a DNL and INL of 0.8/-0.5 and 1.1/-1.5 LSB respectively. The dynamic performance is characterised by 62dB SNDR (10.0 ENOB) at 10MS/s, which is maintained up to 9.5ENOB level for a sampling speed of up to 250MS/s. The power consumption is 6.9pJoule per conversion (70µWatt at 10MS/s, 1.7mW at 250MS/s), resulting in an energy efficiency of 7 to 10fJoule per conversion-step.