To address the challenges that come with advanced-node FinFET designs, the Cadence Virtuoso Advanced-Node Platform is said to allow designers to better manage complexity and process effects.
The platform supports more than four multi-patterned layers for design decomposition; designers can address parasitic and electro-migration (EM) effects during the design cycle rather than wait until designs are completed; it provides support for in-array routing, reducing design iterations; new design rules simplify layout creation and minimise colouring errors that can be pervasive when designing on the 10nm process; and it enables layout engineers to detect and fix errors as designs are being implemented, which can greatly reduce design rule errors while improving overall designer productivity.
Tom Beckley, senior vice president and general manager, Custom IC and PCB Group at Cadence, said: “The new features included with the Virtuoso Advanced-Node Platform can enable our customers to achieve the best possible results, and we already have several customers using it in production design starts to reduce the overhead inherent with 10nm designs.”
