ARM's v8-R architecture to enable new types of MCU?
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Although development of ARM's recently announced v8-R architecture – the real time focused version of the 64bit v8 architecture – has been pushed by the automotive industry, its real time features may enable a new category of microcontroller, according to senior product marketing manager Chris Turner.
"I think it could enable high end real time industrial safety microcontrollers," he told New Electronics at the recent Embedded World exhibition.
However, ARM is still not ready to announce a v8-R based processor core. "I don't think we'll do so this year," said Turner, "but we do have a lot of engineers working on it."
Turner said the architecture is 'stable and well defined'. "We started to talk with tier 1 automotive suppliers and with semiconductor companies about what they needed to see. We found there were a lot of requirements to capture and get exactly right; that made it a significant project."
One of the common areas of feedback focused on determinism. "Cortex-R class cores have a memory protection unit, but not determinism," he continued.
Partly, this is because of there was a lack of gates in the past. "It was something brought forward from ARM9," Turner noted, "and we needed a simpler programming model."
With more gates available and critical paths moving to different places, the v8-R architecture features a more extensive programming model. "We've removed the restriction that the address of a region of memory had to start as a multiple of its size; if you had a 32k region, the first address had to be a multiple of 32 and this created gaps in the memory map. Now, in v8-R, designers can specify any memory size from 64byte upwards and start anywhere."
Turner also pointed to faster context switching. "We've taken thousands of cycles out of each context switch and can now do this in 1 or 2µs; before, it would have been milliseconds and less deterministic. Fast determinism and rigorous isolation between address maps will be a 'big ticket' item."
A v8-R based processor will also be able to run Linux as a guest OS with a memory management unit and a bare metal hypervisor serving safety critical interrupts. "The hypervisor steals cycles from Linux," Turner explained. "Linux carries on not knowing the underlying hypervisor has served an interrupt deterministically in less than 1msec. Mechanical tasks often take tens of milliseconds, so there's plenty of time for cycle stealing."