INTEGRITY-178 tuMP will run on the PU-3000 multicore avionics computer from CMC Electronics, which will be combined with the VDT-1209 video display terminal from Intellisense Systems to form the full C-5M cockpit display system, including the primary flight displays.
The C-5M Super Galaxy is a strategic transport aircraft and is the largest aircraft in the US Air Force inventory. Its primary mission is to transport cargo and personnel.
The C-5M uses multi-function smart displays to provide the pilot, co-pilot, and flight engineers with primary flight and navigation information. The RCMD will use three PU-3000 multicore avionics computers with graphics processing modules installed to drive the new large-format displays. The PU-3000 will also host the C-5M operational flight programme.
The PU-3000 was the first multicore avionics computer to receive TSO authorisation by meeting DO-178C and CAST-32A multicore objectives to the highest Design Assurance Level (DAL A).
The INTEGRITY-178 tuMP safety-critical RTOS is currently the only operating system to be part of a successful multicore certification to DO-178C and CAST-32A objectives. INTEGRITY-178 tuMP is a multicore RTOS with support for running a multi-threaded DAL A application across multiple processor cores in symmetric multi-processing (SMP) or bound multi-processing (BMP) configurations, as well as supporting the more basic asymmetric multi-processing (AMP). INTEGRITY-178 tuMP was the first RTOS to be certified conformant to the FACE Technical Standard, edition 3.0, and it is the only RTOS with multicore interference mitigation for all shared resources, enabling the system integrator to meet CAST-32A objectives.
Multicore interference happens when more than one processor core attempts simultaneous access to a shared resource, such as system memory, I/O, or the on-chip interconnect.
To further ease compliance to CAST-32A, Green Hills provides bandwidth allocation and monitoring (BAM) functionality in INTEGRITY-178 tuMP that ensures that critical applications get their allocated access to shared resources in order to meet their required deadlines, significantly lowering integration and certification risk.
Together, the flexible multi-processing architecture and multicore interference mitigation enable a system integrator to maximize multicore processor performance while meeting safety and security requirements.
