The certification ensures mutual customers of the two companies will have immediate access to a highly automated circuit design, layout, signoff and verification flow to efficiently design products for automotive, mobile, data centre, artificial intelligence (AI) and other emerging applications at 3nm.
When designing for the 3nm GAA process, the Cadence Virtuoso layout flow is able to provide a high level of automation and integration, enabling faster design closure with reduced numbers of iterations.
The tools in the flow incorporate key features that are well suited for digitally assisted analogue designs such as high performance, best-in-class analysis and verification capabilities developed in the Cadence Spectre Accelerated Parallel Simulator (APS). In addition, the Innovus Implementation System and the Cadence digital suite are enabled for the Samsung 3nm process node, allowing customers to implement larger, more complex digital blocks.
The complete, certified custom and AMS flow includes the Virtuoso ADE Suite, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Layout Suite Electrically Aware Design (EAD), Spectre X Simulator, Voltus-Fi Custom Power Integrity Solution, Quantus Extraction Solution, Litho Physical Analyzer (LPA), LDE Electrical Analyzer (LEA), Innovus Implementation System, and Pegasus Verification System.
- Schematic migration
- Circuit design and verification
- Analog layout
- Physical verification and sign-off
- Custom digital and P&R digital layout
“In collaboration with Samsung, we’ve achieved certification for our integrated AMS flow at 3nm GAA to drive continued advancements with next-generation design work,” said KT Moore, vice president, product management in the Custom IC and PCB Group at Cadence. “Based on our leading Virtuoso and Spectre platforms, the flow enables highly efficient AMS designs so our mutual customers can quickly complete complex 3nm designs to meet the needs of evolving end-markets, including automotive, AI, and 5G.”
