Cadence launches first wide I/O memory controller IP solution

It has been designed to enable up to four times the performance of conventional memory interfaces and includes optimisations such as traffic reordering and several low power. Wide I/O, a memory interface standard in review at JEDEC, defines a 512bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8GB/s, which is up to four times the performance of conventional low power memory solutions. The wide I/O interface allows low cost and low power connections between an application processor and the DRAM stacked on top of it. The result is a system that can achieve higher bandwidth with less power while also suitable for reduced pcb area and component height. "We understand that customers not only need robust IP, but also require sophisticated technologies and methodologies for successful integration into a design," said Vishal Kapoor, pictured, vice president of marketing for the SoC Realization Group at Cadence. "The Denali acquisition has given us access to over a decade of experience in advanced memory and storage controller IP. When combined with our exceptional 3D IC technologies and services, we give mobile designers a holistic, proven approach to the development of differentiated SoCs that meet the unique space, performance and power requirements of mobile systems." According to Cadence, the IP is already in use by a high profile customer on two separate projects. Designed to enable maximum system level performance, the wide I/O memory controller includes advanced algorithms to provide efficient data transfer and to schedule transactions. This, says Cadence, delivers 'unprecedented' sustained and peak performance for mobile applications. The IP has the capability of reordering traffic by monitoring system transactions and delineating between low priority and system critical tasks.