Cadence upgrades verification solution, claims x5 improvement
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Cadence Design Systems has launched the Quantus QRC Extraction Solution, said to speed progress to design closure in complex devices by up to five times.
KT Moore, senior director of Cadence's digital and signoff group, said: "This launch is important because customers are looking for new ways to differentiate their silicon – asking such questions as can we add more IP, can we go to a new process or do we need better performance?'. What happens is that verification becomes more complex. An x5 improvement in performance is important to customers; it's beyond the tipping point at which they say 'let's make the change'."
Quantus QRC Extraction Solution, which supports SoC and custom/analogue designs, includes a foundry certified random walk field solver called Quantus FS. Quantus QRC Extraction Solution is said to use the modelling engine from the previous generation product, ensuring compatibility for existing users of QRC Extraction. The tool also provides enhancements to support FinFETs.
Meanwhile, Quantus QRC Extraction has been shown to have the tightest correlation to foundry 'golden data' at TSMC. Suk Lee, senior director of TSMC's design infrastructure marketing division, noted: "Quantus QRC Extraction delivers a solution for FinFET designs that meets TSMC's certification requirements and we will continue our collaboration with Cadence on future technologies."
