Collaboration develops better transistor switching

In its first collaborative work with Hitachi Central Research Laboratory, researchers at the Advanced Technology Institute of the University of Surrey have experimentally and theoretically demonstrated that, for transistors of disordered silicon films, superior switching performance (low leakage current, and steep sub threshold slope) can be achieved by making the conduction channel in the transistor very thin. A higher Ion/Ioff ratio, which exceeds 10exp11, can be achieved for devices with a 2nm thick channel. Another work from the same laboratory addresses the source gated transistor (SGT) concept developed by Professor John Shannon. Compared to a field effect transistor, SGTs can operate with very short source-drain separations, even with a thick gate insulator layer, to achieve high speed, good stability and superior control of current uniformity, providing a significant advantage in terms of the fabrication process. Dr Xiaojun Guo, one of the lead investigators, comments: “Engineering of the transistor structure itself, rather than the channel material, can lead to improved device performance. It will enable the design of high performance large area circuits and systems based on low cost reliable material processes.” Professor Ravi Silva, director of the Advanced Technology Institute added: “This work will help extend the already well established cmos fabrication technologies for use in large area applications such as displays and sensors, which are at the heart of consumer electronics. The ATI is fortunate in that we have been at the forefront of two potential technologies that can lead to enhanced device performance in disordered materials by clever nanoscale structural design of disordered transistors. This type of work sponsored by the EPSRC forms the bedrock for future electronic technologies.”