Digital Core Design presents DAES XTS cryptographic CPU

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DCD, a developer of cryptographic solutions, has announced the launch of the DAES XTS.

Described by the company as a ‘revolutionary’ lightweight cryptographic co-processor, this advanced hardware has been designed to seamlessly implement the Rijndael encryption algorithm in compliance with FIPS 197 Advanced Encryption Standard, specifically tailored for XTS mode as per IEEE Std 1619-2007 standards.

The DAES XTS IP Core addresses the need for robust hardware disk encryption in IoT and embedded devices applications, according to Jacek Hanke, DCD CEO. “With a specialised focus on supporting encrypted memories such as FLASH or RAM, the co-processor features a unique random data access block function, making it an optimal choice for securing sensitive data.”

Deploying the AES block cipher, the DAES XTS offers a number of security and performance benefits over software-based solutions. Its hardware-centric design positions it as a key player in securing environments ranging from IoT devices to cloud servers.

It is important to highlight that, in its current state, Ciphertext-Stealing mode is not supported. Therefore, users should ensure memory sectors are aligned to multiples of 128-bit blocks when implementing the DAES XTS.

In addition, the DAES XTS seamlessly integrates with a diverse range of SPI memory controllers, enhancing its adaptability and compatibility across various applications. This strategic integration amplifies the co-processor's effectiveness and broadens its application scope.