A University of Michigan (UM) team has performed extensive research on near- and sub threshold design over the past decade. The technique reduces the supply voltage very close to or even less than transistor switching voltage. While logic speed can slow dramatically, it can bring large energy savings – as long as leakage does not increase too much.
Nathaniel Pinckney, nVidia research scientist and lead author for the UM work, told last week’s Design Automation Conference in Austin: “Because of short channel effects, the drop off in efficiency in planar technologies down to 20nm was significant. But, now with finFETs, the trends have reversed. Voltage scaling was looking worse and worse, but with the shift to finFETs, it’s looking better and better.”
Working with ARM, the UM team compared three planar and three FinFET technologies and found FinFET circuits designed for slow operation and very low energy consumption were up to three times more effective at much lower voltages than the best 20nm planar designs and that performance increased as the process moved to 7nm.
