First test solution for PCI Express 3.0 receiver characterisation announced
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Agilent Technologies has announced what it claims to be the industry's first test set for PCI Express 3.0 receiver characterisation. The Agilent PCIe 3.0 receiver characterisation test solution has been designed to provide complete and accurate receiver tolerance test results while minimising R&D effort. According to Agilent, it enables users to accurately characterise and verify standard compliance of receiver ports in asics and chipsets.
The PCI-SIG recently released Revision 3.0 of the PCIe base specification. Many changes in the physical layer specification are related to ensuring proper bit transmission at 8GT/s over inexpensive pc boards. Receiver tests are normative now; in previous versions of the standard, these tests were merely informative.
Devices operating at 8GT/s present new measurement challenges that require new tools and procedures to accurately validate receiver design. These challenges include optimising transmit and receive equalisation, calibration channel design and device link training with 128/130bit coded pattern sequences. One of the most challenging requirements is implementing a new procedure for calibrating PCIe 3.0 stress conditions as a reference receiver would see them after applied equalisation. The procedure requires engineers to post-process signals measured at an accessible test point.
Agilent's PCIe 3.0 receiver test solution is based on the J-BERT N4903B high performance serial BERT, the N4916B de-emphasis signal converter, the 81150A pulse function arbitrary noise generator, an Infiniium 90000 X-Series high performance oscilloscope, new accessories and new N5990A test automation software.
"Agilent's new PCIe 3.0 receiver tolerance test solution fills a critical need of asic and chipset designers for rolling out the next generation of PCI Express smoothly," said Jürgen Beck, general manager of Agilent's Digital Photonic Test Division. "By adding our expertise in accurate stress calibration and receiver tolerancing, we continue to help R&D teams efficiently release robust, next generation chipsets for the computer industry."
