FPGA family offers dual configuration

Shelley Davis, director of strategic marketing at Altera, said the new product was both a CPLD and an FPGA. "It combines the best of both in a small package at low cost," she noted. Altera claims the device can result in improved reliability, as well as reduced BOM costs, time to market and board space, by integrating in a single chip such capabilities as: integrated power regulator, up to 500 user I/O Analogue to digital converters, embedded processing with soft-core Nios II processors, embedded memory and DSP blocks, up to 50K logic elements, and flash memory blocks. Davis continued: "The really cool thing is the dual configuation path." This is supported in the on-die flash storage and allows two FPGA designs in a single chip. The dual-configuration capability enables the device to perform fail-safe upgrades, whereby one flash block is designated for upgrade images while the other block is reserved for a 'safe' factory image. The device has an integrated temperature sensor which will appeal to designers in industrial applications. Other applications include machine vision, motor control, automotive infotainment, e-vehicles, communications, computing and storage. Unlike so many 'introductions' in the FPGA market, the launch of MAX 10 is not a 'pre-aanouncement'. It is available now along with tool and evaluation kits, which start at $30. The devices cost around $1.50 in volume. There are 7 devices in the Max 10 family in total and configurations range from 2000 – 50000 logic elements, block memory 108 – 1638kB, and user flash 96 – 512kB. Other families completing the Generation 10 portfolio will be the Arria 10, the company's highest performance 20nm FPGA and Soc which according to Davis is 'coming very soon', and in 2015 the set will be completed with the Stratix 10. This device will use Intel's 14nm Tn-gate process.