Designed for the high-performance and low-power requirements of artificial intelligence (AI), cloud computing, and mobile system-on-chips (SoCs), the production-ready flow is based on the silicon-proven RTL-to-GDSII 12LP foundry reference flow and incorporates Synopsys Advanced Fusion technologies for best quality-of-results (QoR) and time-to-results (TTR) in FinFET designs.
"We want to ensure that GF customers that want to use our differentiated FinFET technology for their next-generation chip designs have the easiest possible path to implementation and production," explained Richard Trihy, vice president, Engineering and Design Enablement at GF. "GF's 12LP FinFET platform delivers a 10 percent improvement in logic density and more than a 15 percent improvement in performance. This, combined with the QoR and TTR advantages provided by the Synopsys Fusion Design Platform, enable our mutual customers to differentiate their products in artificial intelligence, cloud computing, and high-end consumer SoCs."
The Synopsys Fusion Design Platform uses the latest enhancements in the digital implementation and signoff flow to maximize GF's 12LP performance and power benefits. Advanced RC modeling and pin access optimisation in Design Compiler Graphical and Design Compiler NXT synthesis solutions will enable tighter correlation with IC Compiler II place-and-route, leading to faster design convergence.
Logic restructuring, a key feature of Advanced Fusion Technology, enables fast area, timing, power, or congestion-based re-synthesis. ECO Fusion reduces the need for excessive engineering change order (ECO) iterations by allowing rapid design changes during the physical implementation, resulting in faster timing convergence.
The key tools and technologies of the Synopsys Fusion Design Platform certified for GF's 12LP FinFET platform include:
- IC Compiler II place-and-route with Advanced Fusion Technology: Fully automated flow with comprehensive GF 12LP rules support. Deployment of advanced legalizer, pin density-aware placement, total power optimization, logic restructuring, and ECO closure.
- Design Compiler Graphical and Design Compiler NXT RTL synthesis: Advanced power, performance, and area (PPA) optimizations, congestion reduction, pin access-aware optimization, tight correlation, and physical guidance for IC Compiler II.
- IC Validator physical signoff: Physical signoff including DRC, LVS, and Fill. Innovative Explorer DRC and Live DRC technologies for enhanced productivity.
- PrimeTime timing signoff: Advanced variation modeling for low voltages, and enhanced ECO technologies with support for new physical design rules.
- StarRC extraction signoff: Advanced modeling to handle the complexity of FinFET devices, as well as a common technology file for parasitic extraction consistency from synthesis to place-and-route to signoff.
"Synopsys and GF have a long-standing collaboration focused on enabling our mutual customers with proven technologies to deliver innovative next-generation chip designs," said Michael Sanie, vice president of marketing and strategy for the Design Group at Synopsys. "Through the qualification of Synopsys' Fusion Design Platform on a production ready flow, companies creating chips for AI, cloud, and high-end consumer applications can now have the confidence and ability to meet their aggressive time-to-market windows."
