Available now, Version 1.20 adds support for the base instruction set RV32E and also the standard extension for Atomic operations (A).
One of the benefits of using RISC-V is the flexibility associated with the architecture which enables OEMs as well as SoC vendors to design custom cores with the exact definitions needed for the application or product. By continuously adding more support and functionality, IAR Systems makes it possible for these companies to make full use of the capabilities of the leading embedded development toolchain for developing applications based on custom cores.
Through optimisation technology, IAR Embedded Workbench is able to help developers ensure the application fits the required needs and optimise the utilization of on-board memory.
Version 1.20 of IAR Embedded Workbench for RISC-V adds support for the base instruction set RV32E that targets smaller embedded devices with the register set reduced to half of what is available in RV32I. The standard extension for Atomic operations (A) adds instructions that support atomic read, modify, and write actions to support synchronization between different HW processes that access the same memory.
“The more features we add to IAR Embedded Workbench for RISC-V, the more designers can benefit from fully utilizing the quality, reliability and performance that distinguish our complete IDE,” commented Anders Holmberg, Chief Strategy Officer, IAR Systems. “If you add that we are able to offer professional support and training with access to our specialists, you get a powerful tool with excellent support.”.
RISC-V is a free and open instruction set architecture (ISA) based on established Reduced Instruction Set Computing (RISC) principles.
In May 2019, IAR Systems released the first version of IAR Embedded Workbench for RISC-V.
