IMEC makes progress on cmos scaling
1 min read
Belgian research centre IMEC has achieved 'promising results' in its work to scale cmos to the 22nm process node and beyond. The centre says its transistor scaling programs have shown a successful integration of the laser anneal technique in a high K/metal gate (HKMG) process, while it has made a step towards fabricating aggressively scaled germanium pFET transistors.
To scale cmos technology to 22nm and beyond, HKMG is considered as one of the best options. One HKMG integration scheme is metal inserted polysilicon (MIPS). With a MIPS cmos process flow, IMEC has compared spike anneal and laser anneal. For the first time, IMEC has shown functional ring oscillators with millisecond anneal only that show a similar performance as oscillators made using spike anneal.
According to IMEC, the major advantage of laser anneal over spike anneal is that it limits the diffusion of dopants into the Si. This, in turn, helps to keep short channel effects under control as transistors shrink.
Although laser anneal is described as 'challenging', IMEC says the results point to optimisations of the process that will limit defects, maintain a low gate resistance and show effective work function control.
IMEC is also exploring the use of high mobility materials to boost the carrier mobility of mos transistors. This work, which has focused on germanium mosfets, has shown that, using conventional processes, it is possible to make Ge pFET devices with a hole mobility that is substantially greater than the hole mobility curve of silicon.
IMEC said a shallow trench isolation module integrated in a 70nm Ge-pFET allowed scaling to 0.85nm. The results are said to pave the way for further optimisation of Ge pFET devices and for their introduction in high performance chips.
