With a high endurance (1011 cycles), high final remnant polarization (2PR = 30µC/cm2 at 1.8MV/cm) and reduced wake-up, researchers were able to obtain this unique combination of properties by interfacial oxide engineering of the ferroelectric capacitor material stack.
According to imec, this high-performance, scalable, CMOS-compatible ferroelectric capacitor technology will be crucial for enabling FeRAM-based embedded and standalone memory applications.
FeRAM is a class of non-volatile memories with the potential to be used as an embedded memory or as a storage class memory (SCM), as such filling the gap between fast DRAM (~10ns access time) and highly dense NAND Flash.
FeRAM has a DRAM-like 1-transistor-1-capacitor (1T1C) cell architecture, in which the capacitor’s dielectric is replaced with a ferroelectric material to achieve non-volatility. This ferroelectric material can be in two different polarization states (+P and -P) that can be reversed with an external electric field. For several years, much attention has gone to HZO as a ferroelectric since it is compatible with CMOS processing and scalable below 10nm.
Several characteristics come into play to qualify as an embedded or standalone SCM. Ideally, the capacitor of the FeRAM memory cell has a high endurance (>1012 switching cycles) in combination with a remnant polarization 2PR of 30-40µC/cm2 during the entire lifetime. So far, such a combination has never been reported because the capacitors suffer from either a prolonged wake-up (small 2PR in the beginning) or fast fatigue (rapidly degrading 2PR).
“By interfacial oxide engineering, adding both a 1nm TiO2 seed layer and 2nm Nb2O5 cap layer to the La:HZO layer, we achieved for the first-time high endurance (1011 cycles) in combination with a final 2PR as high as ~30µC/cm2 (at an applied electric field of 1.8MV/cm) and good initial 2PR,” explained Jan Van Houdt, programme director of ferroelectrics and fellow at imec. “Following an initial understanding, contact with the Nb2O5 capping facilitates the transition to the desired orthorhombic phase of HZO (i.e., the ferroelectric phase) by injecting oxygen into the HZO layer, while the TiO2 layer favours the preferred (002) grain orientation further resulting in a higher initial 2PR.”
Alternatively, using a different precursor for depositing the HZO layer, a record-high 2PR of 66.5µC/cm2 at 3MV/cm was obtained, though with an endurance of 106 cycles.
“Now we have a high-performance, scalable, and CMOS-compatible ferroelectric capacitor technology that will bring us to the next exciting phase, i.e., moving from planar to 3D FeRAM capacitor structures – leveraging atomic layer deposition (ALD) processes,” added Van Houdt. “This will increase the density needed to bring FeRAM memories to the market as a new embedded or standalone memory.”
