Innovative stacked chips cut development time and costs

The new technology is said to allow electronics designers to stack chip modules with different functions on top of each other, saving space and resources on a carrier board. According to CIC, the MorPACK technology can cut down chip development time from 6–9 months to 2–3 months and reduce development costs of each project by as much as $508,600. Six universities are already using the technology for research and development projects. Huang Chun-ming, head of the development team, said it can be applied to developing chips for any electronic devices, including communications, security, medicine or recreation gadgets. Traditionally, electronic devices need different chips to function and each chip is composed of different modules. Using this technology, developers can stack up different modules into one chip instead of laying out modules separately, which would occupy too much space on a carrier board. "We used the concept of building blocks," Huang said. "This not only saves board space, but also boosts performance because the circuits are closer to each other." Although still in its prototype phase, this new chip technology already has three patents and is applying for another eight worldwide. It is expected to be available by the second half of 2011.