Intel, Numonyx announce stacked PCM test chip

The research team has demonstrated a 64Mbit test chip that has the potential to support multiple layers of PCM arrays within a single die. These work is said to pave the way for memory devices with greater capacity, lower power consumption and optimal space savings. However, the test chip only features a single layer. Al Fazio, director of memory technology development for Intel, noted: "We were going after technology that could scale, with low latency and high bandwidth. This is important, because it enables future memories where you start to combine memory and storage semantics, collapsing them into one technology." Greg Atwood, Numonyx' senior technology fellow, said: "We have demonstrated that PCM can hold its state down to 5nm. In theory, we will achieve the density of NAND with increases according to Moore's Law." The vertically integrated memory cell – called PCMS (phase change memory and switch) – is comprised of one PCM element layered with an Ovonic Threshold Switch (OTS) in what is said to be a true cross point array. Stacking arrays of PCMS provides the scalability to higher memory densities while maintaining the performance characteristics of PCM. Memory cells are built by stacking a storage element and a selector, with several cells creating memory arrays. Intel and Numonyx researchers deployed a thin film, two terminal OTS as the selector, matching the physical and electrical properties for PCM scaling. Because the materials used in their construction are compatible, multiple layers of cross point memory arrays can be created. Once integrated and embedded in a cross point array, layers are combined with a cmos substrate, which handles decoding, sensing and logic functions.