The modules are designed to power the next generation of high-performance computing and AI applications.
To that end, JEDEC has unveiled key details about its upcoming standards for DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMM) and a next-generation Compression-Attached Memory Module (CAMM) for LPDDR6. The new MRDIMM and CAMM for LPDDR6 offer unparalleled bandwidth and memory capacity.
DDR5 MRDIMMs are an efficient new module design to enhance data transfer rates and overall system performance. Multiplexing allows multiple data signals to be combined and transmitted over a single channel, effectively increasing the bandwidth without the need for additional physical connections and providing a seamless bandwidth upgrade to enable applications to exceed DDR5 RDIMM data rates.
Other planned features include:
· Platform compatibility with RDIMM for flexible end-user bandwidth configuration
· Utilisation of standard DDR5 DIMM components including DRAM, DIMM Form Factor & Pinout, SPD, PMIC, and TS for ease of adoption
· Efficient I/O scaling using RCD/DB logic process capability
· Leverage existing LRDIMM ecosystem for design and test infrastructure
· Support for Multi-generational scaling to DDR5-EOL
The JEDEC MRDIMM standard is set to deliver up to twice the peak bandwidth of native DRAM, enabling applications to surpass current data rates and achieve new levels of performance. It maintains the same capacity, reliability, availability, serviceability (RAS) features as JEDEC RDIMM.
According to the committee it aims to double the bandwidth to 12.8 Gbps and increase the pin speed. MRDIMM is envisioned to support more than two ranks and is being designed to utilise standard DDR5 DIMM components ensuring compatibility with conventional RDIMM systems.
Plans are underway for a Tall MRDIMM form factor to offer higher bandwidth and capacity without changes to the DRAM package. This taller form factor will enable twice the number of DRAM single-die packages to be mounted on the DIMM without the need for 3DS packaging.
As a follow-on to JEDEC’s JESD318 CAMM2 Memory Module standard, JC-45 is developing a next-generation CAMM module for LPDDR6 targeting a maximum speed greater than 14.4 GT/s. As planned, the module will also offer a 24-bit subchannel, a 48-bit channel and a connector array.
Both projects are in development in JEDEC’s JC-45 Committee for DRAM Modules.
