Lattice announces Version 1.1 of its Diamond fpga design software
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The update is said to include support for the new MachXO2 PLD range, completion of support for the LatticeECP3 fpga series, and the release of Lattice's own synthesis engine with support for the MachXO and MachXO2 product ranges.
The Lattice Diamond 1.1 design software reportedly includes the initial customer beta release of the Lattice Synthesis Engine (LSE), which is integrated into the software as a synthesis tool choice for design exploration. LSE is said to support both Verilog and VHDL languages and uses SDC format for constraints. According to Lattice, it has several design flow enhancements that include faster recalculation of static timing analysis in the timing analysis view.
Once downloaded and installed, it can be used with either the Lattice Diamond free license or the Lattice Diamond subscription license.
"We have had an extremely positive response from existing and new customers to the Lattice Diamond design environment," said Mike Kendrick, Lattice's Manager of Software Product Planning. "Design exploration targeting low power and cost sensitive applications is further broadened for the MachXO2 PLD user with a choice of synthesis tools."
