Lattice launches MachXO3 fpga range
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Lattice has launched the MachXO3 fpga family, said to be a small, low cost programmable platform aimed at expanding system capabilities and bridging emerging connectivity interfaces.
The family, which spans from 640 to 22,000 logic cells, is manufactured on a 40nm process and delivered in 2.5 x 2.5mm wafer level chip scale packages. Despite the small size, devices with up to 540 I/O are available, as are devices with 3.125Gbit/s serdes interfaces. Clock rates of up to 150MHz are supported.
The company says that, by matching small footprint packaging with on chip resources, the MachXO3 family 'puts affordable innovation into the hands of system architects' by simplifying the implementation of interfaces such as MIPI, PCIe and gigabit Ethernet.
"The MachXO3 family allows designers to address the disparity among the components within their systems with minimal impact on cost, footprint, and power consumption," said Brent Przybus, senior director of product and corporate marketing. "As system performance and complexity increases, I/O interfaces often become the bottleneck.
"Designers want to use the most advanced components, but have to deal with any number of interface standards, many of which are still evolving or are new to many designers, such as MIPI."
