Lattice unveils first low cost fpga to support Broadcom HiGig Protocol

The HiGig MAC IP core is part of the company's LatticeECP3 fpga family and multiple individual devices interconnected via the HiGig protocol operate as one logical network. The HiGig MAC is designed to ensure that the Media Access rules specified in the 802.3ae IEEE standard and HiGig Protocol definitions are met while transmitting a frame of data over Ethernet. On the receive side, it extracts the different components of a frame and transfers them to higher applications through a FIFO interface. The IP core has a 64bit wide internal data path operating at a maximum frequency of 156MHz on the LatticeECP3 fpga. The core provides XGMII and XAUI interfaces to the PHY layer and supports variable sized packet transmission with fixed sized messaging capability (HiGig2 only). With multicast address filtering and 16bit statistics counters, the core requires approximately 4100 fpga look up tables (LUTs) for HiGig implementations and approximately 4700 fpga LUTs for HiGig2 implementations. "The small footprint HiGig MAC IP core will help designers develop bridging and switching solutions with Broadcom devices," said Lalit Merani, Lattice's senior product marketing manager. "This is another example of how Lattice has responded to the needs of its customers by focusing on low cost and low power design with the LatticeECP3 fpga family." The IP core is supported by the company's IPexpress fpga design tool module, which, according to Lattice, 'significantly reduces' design time by allowing IP parameterisation and timing analysis on a user's desktop. It enables users to customise the library of IP functions, integrate them with their proprietary fpga logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments.