MCU delivers 'highest ARM Cortex-M3 performance'

According to NXP, the LPC1800 is optimised for low power operation at low frequencies, through to 150MHz maximum performance from either Flash or RAM. The dual bank 256bit wide flash memories can be used for concurrent write/read operations, allowing 'golden copy' preservation and prevention of reprogramming mishaps, or used as a single bank of memory. The device also features two new peripherals – a flexible quadSPI interface and a state configurable timer subsystem. "The LPC1800 sets a new performance benchmark for ARM Cortex-M3 microcontrollers," said Geoff Lees, vice president and general manager, microcontroller product line, NXP Semiconductors. "What makes the LPC1800 unique is NXP's innovation in reliable, high performance memory architecture and system peripherals." Designed using NXP's 90nm process technology, the device has been designed to offer faster operation, low dynamic power consumption, and proprietary low leakage optimisation, yielding between 10 and 100 times' reduction in standby modes. NXP says the LPC1800 offers the industry's largest on-chip sram for a Cortex-M3 with up to 200KB provided in multiple banks, each with separate bus master access for higher throughput and individual power down control for low power operation. The dual bank 1MB Flash architecture is said to provide the highest reliability in application reprogramming, and allows for non stop Flash operation. NXP announced that it is the first to provide a seamless high speed interface that will connect with virtually all SPI and quad-SPI manufacturers. The company added that high speed interfacing from quad lane SPI memories at up to 80Mbps per lane provides for much larger off chip data and code execution than available from on chip memories.