According to Micron, this new 176-layer technology and advanced architecture represent a radical breakthrough, enabling immense gains in application performance across a range of storage use cases spanning data centre, intelligent edge and mobile devices.
“Micron’s 176-layer NAND sets a new bar for the industry, with a layer count that is almost 40% higher than our nearest competitor’s,” said Scott DeBoer, executive vice president of technology and products at Micron. “Combined with Micron’s CMOS-under-array architecture, this technology sustains Micron’s industry cost leadership.”
The device represents Micron’s fifth generation of 3D NAND and second-generation replacement-gate architecture and the176-layer NAND is said to be the most technologically advanced NAND node in the market.
Compared with the company’s previous generation of high-volume 3D NAND, Micron’s 176-layer NAND improves both read latency and write latency by more than 35%, dramatically accelerating application performance. Featuring approximately 30% smaller die size than best-in-class competitive offerings, Micron’s 176-layer NAND’s compact design is intended for solutions using small form factors.
“Micron’s 176-layer NAND enables breakthrough product innovation for our customers,” said Sumit Sadana, executive vice president and chief business officer at Micron. “We are deploying this technology across our broad product portfolio to bring value everywhere NAND is used, targeting growth opportunities in 5G, AI, cloud and the intelligent edge.”
Micron’s 176-layer NAND is intended to serve a broad array of sectors, including mobile storage, autonomous systems, in-vehicle infotainment, and client and data centre solid-state drives (SSDs).
The device offers improved quality of service (QoS), a critical design criterion for data centre SSDs and can accelerate data-intensive environments and workloads such as data lakes, artificial intelligence (AI) engines and big data analytics.
For 5G smartphones, the enhanced QoS can enable faster launching and switching across multiple apps, creating a more responsive mobile experience and enabling true multitasking and full use of 5G’s low-latency network.
Micron’s fifth generation of 3D NAND also features a maximum data transfer rate at 1,600 megatransfers per second (MT/s) on the Open NAND Flash Interface (ONFI) bus, a 33% improvement. The increased ONFI speed leads to faster system bootup and application performance. In automotive applications, this speed will power near instant-on response times for in-vehicle systems as soon as engines are turned on.
In delivering this technology Micron has combined its stacked replacement-gate architecture, novel charge-trap and CMOSunder-array (CuA) techniques. The company's team of 3D NAND experts achieved rapid advancements with the company’s proprietary CuA technique, which constructs the multilayered stack over the chip’s logic - packing more memory into a tighter space and substantially shrinking the 176-layer NAND’s die size, yielding more gigabytes per wafer.
At the same time, Micron has improved scalability and performance for future NAND generations by transitioning its NAND cell technology from legacy floating gate to charge-trap. This charge-trap technology is combined with Micron’s replacement-gate architecture, which uses highly conductive metal wordlines (wordlines are connecting wires to the gate of each NAND memory storage element in a NAND memory array and are used to select, program and erase groups of memory cells in an array of NAND memory) instead of a silicon layer to achieve unparalleled 3D NAND performance. Micron’s adoption of this technology will also enable the company to drive aggressive, industry-leading cost reductions.
Micron’s 176-layer triple-level cell 3D NAND is in volume production in Micron’s Singapore fab and is now shipping to customers,
