The uMCP has been designed to provide high-density and low-power storage to fit on slim and compact midrange smartphone designs and its packaging builds on the company’s innovation in multichip form factors.
Micron uMCPs combine low-power DRAM with NAND and an onboard controller, using 40% less space compared to a two-chip solution. This optimised configuration saves power, reduces memory footprint and enables smaller and more agile smartphone designs.
"Featuring the latest LPDRAM and UFS interface, this solution offers a 50 percent increase in memory and storage bandwidth, while reducing power," said Dr Raj Talluri, senior vice president and general manager at Micro, "Our new uMCP5 package enables mid-range 5G smartphones to operate with ultra-low latency response times and low power modes necessary to support flagship smartphone features such as multiple high-resolution cameras, multiplayer gaming and AR/VR applications."
The uMCP5 uses advanced 1y nm DRAM process technology and what is said to be the world’s smallest 512Gb 96L 3D NAND die. The 297-ball grid array (BGA) package supports two-channel LPDDR5 with speeds up to 6,400Mbps, a 50% performance increase over the previous-generation interface. The package also provides the highest storage and memory density available for uMCP form factors in the market today, at 256GB and 12GB, respectively.
The uMCP is intended as a solution for Micro's LPDDR5 DRAM, its next-generation memory, which addresses the higher memory performance and lower energy consumption demands of 5G networks, which will start deploying globally at scale in 2020.
Micron LPDDR5 allows 5G smartphones to process data at peak speeds of up to 6.4Gbps, which is critical for preventing data-processing bottlenecks.
