Mark Bohr, pictured, Intel senior fellow for logic technology development, told a panel session at this week's International Solid State Circuits Conference that scaling continues to provide cheaper transistors, but added that cost reduction was still needed in order to justify new process technology.
"Innovation has always been part of the scaling process," he said in a briefing ahead of the panel session. "Technologies such as FinFETs and high K metal gate are indispensible parts of what we do."
In fact, Bohr thinks Intel can move to the 7nm node without having to resort to EUV lithography. "I'm not going to say exactly how, because our competitors watch what we do closely." However, he did say that the move would be accomplished, in part, by the use of new materials and structures. "We have published papers on III-V devices," he added, "so that's one example, but introducing any new technology will be about balancing performance against manufacturability."
Bohr also believes that 2.5 and 3D integration will also play an important role, but said it was hard to identify a point where 2.5/3D would become cost effective. But he said the techniques wouldn't be a replacement for Moore's Law. "They don't bring cost reduction, like Moore's Law, which is why they haven't become mainstream. While it adds cost, it's important to recognise the need for heterogeneous integration."
