Because MTJs use magnetic properties, the quality of the surface between the MTJ and its lower electrode is important; if the surface area is not smooth, the electric/magnetic characteristics will degrade. For this reason, says the team, placing an MTJ directly on vias has been avoided, although it increases the size of the memory cell.
Professor Tetsuo Endoh’s group tackled this problem by developing a special polishing process and its effectiveness has been verified by an experiment using a 2Mbit STT-MRAM test chip integrating more than 1million MTJs.
“Not only does this test chip show a 70% improvement in its memory bit yield compared to standard STT-MRAM, but its memory cell area is reduced by 30%,” said Prof Endoh. “It will be very effective for reducing the chip area of MRAM.”
