Called the TILE-Mx, the device – scheduled to sample in 2016 – is built around the Cortex-A53 core and is optimised for data-path throughput and combining high performance management and control-plane processing.
Offering a processing performance of 200Gbit/s, the device will be accompanied by two further members of the family, with 64 and 36 cores.
“We are bringing to the market a new type of highly differentiated multicore processor, leveraging the best from EZchip's and Tilera's technologies, and specifically architected to address the next generation of high-performance data center, cloud and carrier networks," said Eli Fruchter, CEO of EZchip. “The combination of EZchip's and Tilera's market-proven leading technologies enables us to develop a new multicore processors family that uniquely integrate powerful networking capabilities together with the highest number of processor cores to address a wide range of applications and market segments."
