The device comprises a silicon photonics chip, flip chip integrated with a low power 40nm CMOS chip. The photonics chip, fabricated on imec's 25Gbit/s Silicon Photonics Platform, has an array of four 25Gbit/s ring modulators, coupled to a common bus waveguide to allow WDM transmission. On the receive side, a ring based demultiplexing filter with a channel spacing of 300GHz is connected to an array of four 25Gbit/s Ge waveguide photodetectors.
The CMOS chip includes four differential 20Gbit/s ring modulator drivers and four 20Gbit/s transimpedance amplifiers. A 12 channel single mode fibre array is packaged onto the chip's grating coupler array, using a planar approach developed at Tyndall National Institute.
According to the partners, error free operation was demonstrated in a 20Gbit/s loop-back experiment for all four WDM channels, as well as with two channels running together. Dynamic power consumption was found to be less than 2pJ/bit. The partners claim the transceiver can be further scaled to higher bandwidth capacity by adopting more advanced CMOS technology and by adding more WDM channels.
