PHY IP provides 'significant' power savings in USB 2.0 chip to chip connections
A new high speed inter chip (hsic) compatible PHY IP is said to provide 'significant' power and area savings in USB 2.0 chip to chip connections. IP core specialist, Evatronix, says the USBHSIC-PHY logic macro can enable straightforward implementation of the USB 2.0 chip to chip connectivity with all components.
The HSIC technology has been designed to enable a direct connection on a PCB board to be set up between a USB host chip and other on board USB devices. According to Evatronix, the HSIC standard features much less power consumption due to elimination of requirements to support long external USB cables while remaining USB protocol compliant and USB software compatible.
Through the implementation of a 240MHz DDR interface, the HSIC standard provides full support for the 480Mb/s data transfer of the USB protocol. According to Evatronix, by eliminating 3.3 and 5V signaling, the HSIC interface enables 'significant' silicon area and power savings in comparison to standard cable USB 2.0 PHYs.
It is available now on the LFoundry 150nm process with the possibility to port it to any technology node from 65 to 180nm.
