Precision parallel technology delivers up to 7X speed up

The HSPICE 2010 solution includes enhanced convergence algorithms, advanced analogue analysis features and foundry qualified support for process design kits. According to Synopsys, this extends HSPICE accuracy to the verification of complex circuits such as phase locked loops, SERDES, data converters, high precision custom digital and power management. Xiaowei Wang, director of analogue design at HiSilicon, said: "Using the latest HSPICE precision parallel technology on a data converter, we obtained a 7X speed up on eight cores, reducing a multiple day simulation to about 8hours. HPP enables our analogue engineers to improve productivity by simulating multiple iterations of the designs in a single day." The new hpp technology is designed to take multithreading performance to a new level for complex analogue circuits with faster speed and multicore scalability. Synsopsys says HPP combines an adaptive submatrix technology with optimised cache utilisation and streamlined device model evaluation to obtain fast, highly scalable performance on multicore machines. The memory management allows simulation of post layout circuits larger than 10million elements. "With the increasing use of digitally assisted analogue circuits in SoCs, designers are demanding innovation in circuit simulation to significantly speed up transient simulation and to take advantage of the latest multicore compute resources," said Paul Lo, senior vice president and general manager, Synopsys Analogue and Mixed Signal Group. "We continue to invest in new HSPICE technology to improve simulation productivity for the HSPICE user community." The HSPICE Precision Parallel technology is in limited customer availability and will be generally available in December 2010.