With the ability to support data rates of up to 8.4 Gbps, it can deliver over a terabyte per second of bandwidth, more than double that of high-end HBM2E memory subsystems. Already with a strong track record in HBM2/2E memory interface deployments, Rambus is said to be well placed to support customers’ implementations of accelerators using next-generation HBM3 memory.
In addition to the fully-integrated HBM3-ready memory subsystem, Rambus provides its customers with interposer and package reference designs to speed their products to market.
“With the performance achieved by our HBM3-ready memory subsystem, designers can deliver the bandwidth needed by the most demanding designs,” said Matt Jones, general manager of Interface IP at Rambus. “Our fully-integrated PHY and digital controller solution builds on our broad installed base of HBM2 customer deployments and is backed by a full suite of support services to ensure first-time right implementations for mission-critical AI/ML designs.”
The benefits of the HBM3-ready Memory Interface Subsystem include:
- Supports up to 8.4 Gbps data rate delivering bandwidth of 1.075 Terabytes per second (TB/s)
- Reduces ASIC design complexity and speeds time to market with fully-integrated PHY and digital controller
- Delivers full bandwidth performance across all data traffic scenarios
- Supports HBM3 RAS features
- Includes built-in hardware-level performance activity monitor
- Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
- Includes 2.5D package and interposer reference design as part of IP license
- Features LabStation development environment that enables quick system bring-up, characterization and debug
- Enables the highest performance in applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems
