To date, the values obtained are the lowest charge noise values achieved on a 300mm fab-compatible platform and such low noise values enable high-fidelity qubit control, as reducing the noise is critical for maintaining quantum coherence and high-fidelity control.
By demonstrating those values, repeatedly and reproducibly, on a 300mm Si MOS quantum dot process, it should be possible to make large-scale quantum computers based on Si quantum dots.
Si quantum dot spin qubits are promising building blocks when it comes to developing large-scale quantum computers for two main reasons. First, Si spin qubits with long quantum coherence times (a metric reflecting their ability to store quantum information for a long time) and high-fidelity quantum gate operations have been repeatedly demonstrated in lab environments and are therefore a well-established and tested technology with realistic prospects.
Second, and potentially more importantly for the long-term viability, the underlying technology is compatible and intimately linked with CMOS manufacturing technologies and as such offers the possibility of wafer-scale uniformity and yield with the required advanced back-end-of-line interconnection of the Si quantum dot structures that are needed for truly large-scale quantum chips, with millions or even billions of qubits operating in synchrony.
Several types of Si quantum dot spin qubits exist and are being pursued at imec. In this work, the quantum dot spin qubits were defined by metal-oxide-semiconductor (MOS) quantum dot structures that resemble modified transistor structures to trap a single spin of an electron or hole.
To achieve long quantum coherence times, the noise, and in particular the charge noise of the quantum dot should be as low as possible. That noise generally results from residual charges, trapped nearby or even inside the quantum dot, removing those is key to increase the performance of the spin qubits.
Ultimately, this is determined by the full processing stack of the quantum dot qubit structure, since any defects introduced there need to be minimised and while this can be realised through lab-based techniques such as very gentle lift-off processes that reduce process damage, industrial manufacturing techniques like subtractive etch and lithography-based patterning have shown to easily result in degradation of the device and interface quality, particularly at the Si/SiO2 interface nearby the quantum dot qubits.
As a result, the charge noise of Si/SiO2-based quantum dot structures manufactured in professional fabrication facilities is typically higher than the values obtained using lab-based processing.
However, by careful optimisation and engineering of the 300mm Si/SiO2-based MOS gate stack, imec has been able to achieve a record-low average charge noise level of only 0.6µeV/Hz (at 1Hz), across 300 mm wafers and characterized using statistical methods.
Kristiaan De Greve, imec Fellow and Program Director Quantum Computing at imec said, “We demonstrated charge noise levels that, depending on the source, are between half an order of magnitude to one order of magnitude lower, when compared to current state-of-the-art fab-based Si quantum dot structures and achieved remarkably uniform quantum dot operation. Our results confirm that 300mm Si MOS is a compelling material platform for quantum dot spin qubits and highlight the maturity of industrial fabrication techniques for qubit development.”
In addition, the statistical analysis methods used to characterise the low charge noise devices revealed fundamental insights into their origin.
“Knowing the source of the charge noise will give us directions to further optimise the quantum dot structures,” added De Greve. “The low-noise qubit environment and demonstrated uniformity of the CMOS manufacturing are just the start of a series of enabling technology developments for upscaling quantum chips towards eventual practical quantum computing, which, with current understanding, will require millions of physical qubits.”
