SiLabs introduces first 4-PLL clock ICs
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Silicon Laboratories has introduced what it claims are the industry's highest performance and most integrated clock ICs, designed to address the complex timing requirements of high speed optical transport network applications.
SiLabs claims the Si5374 and Si5375 devices, based on its DSPLL technology are the first single chip timing ICs to integrate four independent, phase locked loops (PLLs). According to the company, they provide twice the PLL integration and 40% lower jitter than competing solutions. Each DSPLL clock multiplier can be configured to generate any frequency from 2kHz to 808MHz. This is to help simplify the generation of high speed PHY reference clocks and eliminate the need for discrete VCXO based PLLs currently used in OTU3 and OTU4 applications.
Other features include SONET compatible jitter peaking and a hitless switching capability, designed to minimise output clock phase transients during reference switching. Each DSPLL engine features an integrated loop filter that supports user programmable bandwidths down to 4Hz. The mixed signal/analogue specialist says this enables wander filtering in addition to jitter attenuation, which is configurable on a per channel basis.
"The convergence of high bandwidth data, video and voice services over OTN and increasing optical line card port densities require higher levels of clock integration and ultra low jitter to minimise design cost and complexity," said Mike Petrowski, general manager of Silicon Labs' timing products. "Silicon Labs' new Si537x clock ICs offer more high performance PLL integration than competing solutions at the industry's lowest jitter levels, setting a new benchmark for purpose built OTN clocking solutions."
