ST, MIT unveil ultra low power microprocessor

Implemented in ST's 65nm cmos process, the device is designed to address applications with limited power budget and time varying processing loads in the medical, wireless sensor networks and mobile fields. "This breakthrough technology can enable the development of an entirely new generation of microprocessors for wireless sensors and implantable medical devices, where minimised power consumption and long battery life are absolutely critical," said Alessandro Cremonesi of STMicroelectronics. "Our work with MIT aspires to play a key role in expanding the industry's horizons in ultra low power technologies." The ST-MIT microprocessor SoC is optimised to reduce power consumption to10.2pJ/cycle at 0.54V, while the sram memory cells are said to operate at 0.4V. A small latch based instruction and data caches have been implemented to further reduce memory access power. Additional features include on chip ultra low power clock generation and analogue to digital conversion. The microprocessor also includes a set of peripherals, such as timers and serial interfaces, which are able to work at the minimum voltage supply. "MIT researchers and STMicroelectronics engineers have worked together to develop and implement a number of architectural and circuit techniques to reduce power consumption," said Professor Anantha Chandrakasan (pictured) of MIT. "The energy efficient processor will enable a number of exciting sensor network applications such as embedded bio medical systems."