Having recently completed the porting and testing necessary for system-software like UEFI, BMC, bootloader, and operating systems through the toolchains, Tachyum has now completed porting of other applications to test a wide range of workloads on the FPGA prototype. When applications are verified to run cleanly on the Prodigy FPGA, the Prodigy chip will be ready for tape-out and volume manufacturing.
To accelerate application testing, Tachyum has developed a new infrastructure for regression testing, to capture FPGA execution and bugs in the first instance. Using this system, engineers can avoid manually reproducing bugs, a time-consuming process that can delay development schedules.
This infrastructure is essential for bugs which occur after trillions of cycles, which would take a very long time to debug. Catching bugs on their first occurrence is the key to getting the chip ready for production quickly. Engineers can take traces from the Prodigy FPGA prototype, run trillions of cycles in a C-model called “cyclerun“ and then feed the state from the C-model to the RTL simulation, which can run tens of millions of cycles, or more, before the bug manifests in RTL. The engineers can then debug in the RTL simulation, instead of using a very time-consuming signal tap on the FPGA.
“Validating applications necessarily follows completing the physical design of the chip and will help us verify Prodigy’s performance in customer and partner deployments,” said Dr. Radoslav Danilak, founder and CEO of Tachyum.
The company has also verified Prodigy’s design against the most recent version of the industry-standard Berkeley TestFloat/SoftFloat package.
Prodigy’s architecture unifies the functionality of CPU, GPGPU, and TPU into a single chip and integrates 128 high-performance custom-designed 64-bit compute cores, to deliver up to 4x the performance of the highest-performing x86 processors for cloud workloads, as well as up to 3x that of the highest performing GPU for HPC, and 6x for AI applications.
