Water cooled chip stacks
1 min read
IBM scientists are using water to cool 3d chip stacks. The company claims the approach promises to advance Moore’s Law in the next decade and to reduce significantly energy consumed by data centres.
Working in collaboration with the Fraunhofer Institute in Berlin, the researchers have demonstrated a prototype that pipes water directly between each layer in the stack.
“As we package chips on top of each other to speed a processor’s capability to process data, we have found that conventional coolers attached to the back of a chip don’t scale. In order to exploit the potential of high performance 3d chip stacking, we need interlayer cooling,” explains Thomas Brunschwiler, project leader at IBM’s Zurich Research Laboratory. “Until now, nobody has demonstrated viable solutions to this problem.”
3d chip stacks could have an aggregated heat dissipation of close to 1kW with an area of 4 sq cm and a thickness of about 1mm.
Brunschwiler and his team piped water into cooling structures as thin as 50µm between the individual chip layers in order to remove heat. A cooling performance of up to 180W/cm2 per layer for a stack is claimed.
“With classic backside cooling,” said Bruno Michel, manager of the chip cooling research efforts at the IBM Zurich Lab, “stacking two or more high power density logic layers would be impossible.”
